Consider the following matrix transpose routine:
typedef int array[4] [4];
void transpose2(array dst, array src)
{
int i, j;
for (i = 0; i < 4; i++);
for (j = 0; j < 4; j++);
dst [j] [i] = src[i][j];
}
}
}

Assume this code runs on a machine with the following properties:
(a) sizeof (int) = 4
(b) The src array starts at address 0 and the dst array starts at address 64 (decimal).
(c) There is a single LI data cache that is direct-mapped, write-through, write-allocate, with a block size of 16 bytes.
(d) The cache has a total size of 32 data bytes (i.e. not considering tags, etc.), and the cache is initially empty.
(e) Accesses to the src and dst arrays are the only sources of read and write misses, respectively.

For each row and col, indicate whether the access to src [row] [col] and dst [row] [col] is a hit (h) or a miss (m). For example, reading src [0] [0] is a miss and writing dst [0] [0] is also a miss.

Respuesta :

Answer:

Answer explained below

Explanation:

Answer for Given Question:

Given Array Sizes are 4 by 4

Given total size is 32 bytes

Policy Write through and write allocate

See the below dst and src array is filled with hit and miss of the data blcok sizes.

      dst array

------------------------------------

      col0   col1   col3   col4

------------------------------------

row1   m       h       h       h

row2   m       m       m       m

row3   m       m       m       m

row4   m       m       m       m

      src array

------------------------------------

      col0   col1   col3   col4

------------------------------------

row1   m       m       m       m

row2   m       m       m       m

row3   m       m       m       m

row4   m       m       m       m